In a prior art Schottky barrier gate field effect transistor (hereinafter, referred to as MESFET) utilizing a heat-resistant gate, in order to enhance the high frequency response of the MESFET, a low resistance film is disposed on the heat-resistant gate to reduce the gate resistance.
A prior art production process of this kind of FET structure will be described with reference to FIGS. 3(a) to (d).
First of all, as shown in FIG. 3(a), an active layer 2 is produced in a semiconductor substrate, for example, a semi-insulating GaAs substrate 1, and thereafter a heat-resistant material is plated on the semi-insulating GaAs substrate 1 to produce a heat-resistant gate 3. Next, as shown in FIG. 3 (b), resist 4 is deposited on the entire surface of substrate, and a resist pattern is produced on the heat-resistant gate 3 by photolithography. Thereafter, a low resistance metal material 5' is plated on the entire surface of the substrate as shown in FIG. 3 (c), and is lifted off together with the resist pattern 4, thereby producing a low resistance metal layer 5 on the heat-resistant gate 3 (FIG. 3(d)).
In this prior art production process, however, since pattern alignment of resist pattern 4 is required to plate a low resistance metal 5' after the heat-resistant gate 3 is produced, it was very difficult to produce the low resistance metal layer pattern 5 on a heat-resistant gate 3 of sub-micron length with a high degree of control.